(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes to the formation of MOSFETs (metal oxide silicon field effect transistors).
(2) Background of the Invention and Description of Previous Art
Integrated circuits(ICs) are manufactured by first forming discrete semiconductor devices within the surface of silicon wafers. A multi-level metallurgical interconnection network is then formed over the devices contacting their active elements and wiring them together to create the desired circuits. Most of the ICs produced today utilize the MOSFET as the basic semiconductive device. MOSFETs are chosen over their bipolar counterparts because they can be easily manufactured and, because they operate at low voltages and currents, they generate less heat thereby making them well suited for high density circuit designs.
The basic MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is typically formed by a self-aligned polysilicon gate process wherein source and drain regions are formed adjacent to the polysilicon gate by ion implantation using the gate as a mask. The source/drain is thereby self-aligned to the gate electrode. A channel region directly under the polysilicon gate is thereby also defined by the gate electrode. In order to reduce hot electron injection into the channel region, a low concentration of source/drain dopant is first implanted with the gate as a mask. This is commonly referred to as a lightly doped drain (LDD) implant. Sidewalls are then formed alongside the gate electrode and a second substantially deeper and higher dosage implant is then applied to form the main source/drain regions which are spaced laterally away from the edge of the polysilicon gate by the sidewall thickness. The completed source/drain regions then each consist of a main heavily doped portion to which external contact is made and a lightly doped extended portion which abuts the channel region.
As device dimension continue to shrink, short channel effects become significant and begin to affect device performance. In conventional LDD processes short channel effects are compensated by implanting shallower junctions which come at the expense of high impurity concentrations. As a consequence, the resultant lower impurity concentrations cause undesirably high source and drain series resistance. It is therefore desirable to form shallow LDD regions with highly activated impurity concentrations and abrupt junctions.
Ishida, U.S. Pat. No. 5,966,605 cites a method for infusing dopant into a polysilicon gate structure by first blanket depositing a dopant enriched layer over the wafer after the polysilicon gate structure has been formed. Laser irradiation is then applied to melt the polysilicon and thereby causing the dopant to be infused therein. The laser energy is not sufficient to melt and cause dopant infusion into the source/drain regions. Yu, U.S. Pat. No. 6,372,585 B1 shows that nitrogen, implanted into silicon can be induced to bond within the silicon by pulsed laser annealing. Zhang, et.al., U.S. Pat. No. 6,319,761 B1 shows that annealing of ion implanted source/drain regions with an excimer laser improves crystallinity and repairs implant damage.
Chong, et.al. U.S. Pat. No. 6,365,446 B1, issued to the present assignee, shows a method for simultaneously forming silicide contact regions and source/drain regions by first, amorphizing the designated regions by ion implantation of Ge, As, or Ar, next depositing a refractory metal layer, and then implanting the dopant ions through a metal layer. The amorphized regions are then melted by laser irradiation, causing the dopant atoms to quickly distribute in the melted regions. At the same time, the refractory metal reacts with the upper surfaces of the molten amorphized silicon regions to form a metal silicide. The melted source/drain regions then recrystallize to form active source/drain elements.
In a related patent Chong, et.al. U.S. Pat. No. 6,391,731 B1, amorphize both the deep source/drain regions and the shallow source/drain extensions using two Ge, As, or Ar implantations. After dopant implantation, a single laser anneal then melts these regions and caused the dopant to distribute. After the anneal the regions re-crystallize epitaxially from the subjacent single crystalline silicon to form highly activated, very shallow doped regions with abrupt junctions.
It is found by the present inventors that, while a high degree of activation and superior abrupt junctions are obtained by these measures, junction movement nevertheless occurs during the laser annealing process, wherein the amorphous regions are selectively melted and then recrystallized. This becomes increasingly significant and measurable for ultra shallow source/drain extensions or LDD regions. This is illustrated in FIG. 1 wherein the boron profile is shown before 50 and after a spike rapid thermal anneal 52 and after a single laser melting anneal 54 at a laser energy of 0.4 Joules/cm2 for a pulse duration of about 23 nanoseconds. Estimating the junction begins at a point where the boron concentration diminishes to about 2×108 atoms/cm3, the as implanted junction is at a depth of about 35 nm. After the spike RTA at 1,080 C, the junction has moved to about 58 nm. After the laser anneal the junction depth has essentially doubled, dropping down to about 65 nm. The profile 54 after the single pulse laser anneal is typical and clearly shows the uniform boron distribution which occurs during period when the silicon is molten. The point 56 is believed to be the bottom boundary of the amorphous silicon which is molten during the laser anneal. The boron beyond this point has diffused out of the amorphous region and into the subjacent single crystal silicon during the molten period, resulting in a deeper junction, the junction profile is decidedly more abrupt than the as deposited boron. The sheet resistance recorded for the laser annealed profile shown in FIG. 1 was 215 ohms/square while that of the RTA spike anneal was about 300 ohms/square.
While single pulse laser anneal exhibits a higher degree of activation than the spike RTA anneal, as indicated by the lower resistivity, the increase of junction depth is not a welcome compromise. It is therefore desirable to achieve low resistivity without sacrificing junction depth. The present invention cites an activation annealing procedure which results in a high degree of activation while leaving the as-implanted dopant profile essentially unchanged.